The present invention relates to the threshold of a circuit, and is more particularly related to a circuit in which its threshold may be programmed to be one of several values, as desired.
U.S. Pat. No. 3,449,594 to J. J. Gibson et al. issued June 10, 1969 for "Logic Circuits Employing Complementary Pairs of Field-Effect Transistors" discloses gate circuits having two conduction paths, each conduction path including two field-effect transistors of different conductively types having their source-to-drain channels connected in series.
U.S. Pat. No. 3,900,742 to Hampel et al. issued Aug. 19, 1975 for "Threshold Logic Using Complementary MOS Device" discloses gating circuits having threshold gates which are implemented by CMOS devices.
U.S. Pat. No, 4,217,502 to Suzuki et al. issued Aug. 12, 1980 for "Converter Producing Three Output States" discloses various circuits having field-effect transistors in series-parallel combinations.
U.S. Pat. No. 4,438,352 to Mardkha issued Mar. 20, 1984 for "TTL Compatible CMOS Input Buffer" discloses a TTL compatible CMOS input buffer which is accomplished by changing the input high voltage and by changing the drive of the n or p channel transistors or the width of the n channel transistor.
U.S. Pat. No. 4,555,642 to Morales issued Nov. 26, 1985 for "Low Power CMOS Input Buffer Circuit" discloses a low power CMOS input buffer circuit for use with a TTL level input. An additional input buffer "dummy" is included to sense and compare the input voltage to CMOS logic levels, and to compensate the input voltage if needed.
Other patents of interest include: U.S. Pat. No. 4,471,242 to Noufer et al. issued Sept. 11, 1984 for "TTL to CMOS Input Buffer"; U.S. Pat. No. 4,518,873 to Suzuki et al. issued May 21, 1985 for "Buffer Circuit for Driving a C-MOS Inverter"; U.S. Pat. No. 4,533,841 to Konishi issued Aug. 6, 1985 for "MOS Logic Circuit Responsive to an Irreversible Control Voltage for Permanently Varying its Signal Transfer Characteristic"; U.S. Pat. No. 4,578,600 to Magee issued Mar. 25, 1986 for "CMOS Buffer Circuit"; U.S. Pat. No. 4,584,491 to Ulmer issued Apr. 22, 1986 for "TTL to CMOS Input Buffer circuit for Minimizing Power Consumption"; and U.S. Pat. No. 4,593,212 to Svager issued June 3, 1986 for "TTL to CMOS Input Buffer".